1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process designed to improve surface planarity of polysilicon gate layers.
2. Background Information
In order to fabricate high performance metal oxide semiconductor (MOS) transistors, it is crucial to control gate electrode linewidths. Improved control of the gate electrode linewidth allows the formation of smaller channel lengths and increases the performance of MOS transistors. Non-planar polysilicon layer surfaces degrade the ability to control linewidths during lithographic processing for gate patterning. This degradation of control is generally due to variations in photoresist thickness and irregular light reflections off the polysilicon surface.
Polycrystalline silicon (polysilicon) is a preferred gate electrode material for MOS devices because it is easy to deposit and easy to dope. Polysilicon, however, also has disadvantages that interfere with lithographic patterning and decrease linewidth control. One disadvantage is that polysilicon, due to its grain structure, forms a relatively rough surface layer. Another disadvantage is that the remaining topography from the underlying isolation structures is replicated in the polysilicon surface. Both of these disadvantages interfere with lithographic patterning and degrade linewidth control.
FIG. 1a illustrates a cross sectional view of polysilicon layer 130 deposited above thin gate oxide layer 120, isolation regions 110 & 111, and substrate 100. The rough surface of polysilicon layer 130 caused by the grain structure of polysilicon is also illustrated in FIG. 1a. Additionally, the underlying topography of isolation regions 110 & 111 and substrate 100 are replicated in the surface of polysilicon layer 130. The rough surface and the underlying topography in polysilicon layer 130 cause reflection and scattering effects during photolithographic patterning of a photoresist.
FIG. 1b illustrates a cross sectional view of mask 150 and photoresist layer 140 coated on the polysilicon layer 130 of FIG. 1a. It is a well known process in the art to pattern polysilicon gate layers using a patterned photoresist. In order to pattern photoresist layer 140, mask 150 is used to block the light. As shown in FIG. 1b mask 150 only covers a portion of photoresist layer 140. The uncovered regions of photoresist layer 140 are exposed to light. Exposure to light causes the uncovered portions of photoresist layer 140 to become soluble. FIG. 1b illustrates mask 150 and photoresist layer 140 being exposed to light. Because the light rays are being reflected and scattered by the rough surface and underlying topography of polysilicon layer 130, regions of photoresist layer underlying the mask are exposed to light and become soluble.
The step height difference caused by underlying topography results in variations in the photoresist thickness as it covers the topography. This variation in photoresist thickness also contributes to increased variation in the linewidth control of the patterned photoresist layer due to thin film interference effects. In other words, when a thin photoresist film is exposed to light, internal reflection and interference can affect the light intensity thus degrading linewidth control.
After photoresist layer 140 has been subjected to a developing solution only the insoluble portions of photoresist layer 140 remain, as shown in FIG. 1c. The insoluble portions of photoresist layer are the portions of photoresist layer 140 not exposed to light. Due to the reflection and scattering of the light by polysilicon layer 130, photoresist layer 140 is poorly patterned. The features of photoresist layer 140 have poor edge definition and have varying horizontal dimensions.
The patterned photoresist is then used to pattern the polysilicon layer 130 into a gate electrode. Polysilicon gate layer 130 is patterned using well known etch techniques, such as, reactive ion etch (RIE), to form a polysilicon gate electrode as shown in FIG. 1d. Because the patterned photoresist layer 140 (in FIG. 1c) has wavy edges and varying horizontal dimensions, the gate electrode 130 in FIG. 1d is formed with poor edge definition and varying linewidth. Therefore, the poorly patterned photoresist layer can cause the gate electrode to be formed with varying gate-lengths. FIG. 1e illustrates a top view of the gate electrode 130 in FIG. 1d.
The variation in gate-length of the gate electrode can cause variations in channel length. Variation of the channel length varies the electrical characteristics of an MOS device and must be carefully controlled.
Presently there are two techniques for improving gate electrode linewidth control in the manufacture of high performance MOS transistors. The first technique is known as amorphous silicon deposition. Amorphous silicon deposition eliminates the surface roughness caused by the grain structure of polysilicon but does not eliminate the replication of underlying isolation topography in the polysilicon surface. Additionally, amorphous silicon deposition has problems with deposition defects and is also more difficult to fully dope.
The second technique for improving linewidth control is the use of anti-reflective layers as part of the lithographic process. The use of anti-reflective layers reduces the effects of both the surface roughness caused by the grain structure of polysilicon and the resist thickness variation due to the underlying topography. An anti-reflective layer is highly absorbing and reduces the reflection and scattering effects caused by the rough surface and the topographical features of the polysilicon layer. The addition of an anti-reflective layer also helps to planarize the isolation topography and reduce the variation of the photoresist thickness. Anti-reflective layers, however, require special processing equipment and add additional steps, i.e. depositing and etching the anti-reflective layer. The need for special processing equipment significantly increases the cost of manufacturing the MOS transistors. Also, the additional steps required by the use of anti-reflective layers increases the defect level normally associated with the production of MOS transistors.
Thus, what is needed is a method that removes both sources of non-planarity associated with polysilicon and that improves linewidth control using standard lithographic techniques without increasing the defect level already associated with the manufacture of high performance MOS transistors.